Baldauf, Tim

Professor für Theoretische Elektrotechnik / Optoelektronik

Physik von Halbleiter-Bauelementen Skalierung von Ultra-Kurzkanal-Transistoren Mechanisch verspannte Halbleiter TCAD-Simulationen Rekonfigurierbare Feld-Effekt-Transistoren (RFET)

KoautorInnen‑Netzwerk

Wissenschaftslandkarte

Aktivitäten

Veranstaltungen

A wired-AND transistor: Polarity controllable FET with multiple inputs
Analyse und Optimierung von verspannten Schichten auf CMOS–Transistoren
Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform
In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs
Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels
Simulation and Optimization of Tri-Gates in a 22nm Hybrid Tri-Gate/Planar Process
Suppression of the corner effects in a 22 nm hybrid tri-gate/planar process
High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits (Invited)
Optimization of Stressor Overlayer Parameters for MOSFET's in "Cool Silicon" – Technologies
Strain Analysis for Reconfigurable Silicon Nanowire Devices

Betreute Dissertation

Charakterisierung von niederfrequentem Rauschverhalten (Random Telegraph Noise) hochintegrierter Halbleiterstrukturen

Dissertation

Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie

Projekte

Beteiligungen

Publikationen

ausgewählte Veröffentlichungen

Wissenschaftlicher Artikel
- Improvement of low-frequency noise behavior with chloridic precursor materials at ALD process. Memories - Materials, Devices, Circuits and Systems. 2024
- Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation. IEEE transactions on nanotechnology. 21. 2022
- A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation 2022
- Vertically Integrated Reconfigurable Nanowire Arrays. IEEE electron device letters. 39. 2018
- Enabling Energy Efficiency and Polarity-Control in Germanium Nanowire Transistors by Individually Gated Nano-Junctions 2017
- Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents. IEEE transactions on nanotechnology. 16. 2017
- Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors. Solid-state electronics. 128. 2017
- The RFET-a reconfigurable nanowire transistor and its application to novel electronic circuits and systems 2017
- (Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits. Meeting abstracts (Electrochemical Society). MA2016-02. 2016
- Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors. IEEE transactions on nanotechnology. 14. 2015
- Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors. IEEE electron device letters. 36. 2015
- Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized?
Konferenz-Paper
Tagungsband

Forschung

andere Forschungsaktivitäten

Kontakt

vollständiger Name

Tim Baldauf